Search - adder verilog floating point

[VHDL-FPGA-Verilog] flowadd

Description: 两个浮点数相加的加法器，使用verilog编写-Addition of two floating-point adder, the use of Verilog to prepare
Platform: | Size: 1024 | Author: 蔡大 | Hits:

Description: 6级流水，verilog实现浮点数的加法，其中浮点数格式符合IEEE754标准-6 water, verilog realize the floating point adder, in which floating-point format in line with the IEEE754 standard
Platform: | Size: 2048 | Author: 兰兰 | Hits:

[Linux-Unix] fpadd

Description: 利用verilog hdl编写的浮点加法器运算单元，单精度。-Verilog hdl prepared to use floating-point adder computing unit, single-precision.
Platform: | Size: 12288 | Author: 孟军 | Hits:

[source in ebook] fadd

Description: it is verilog code for floating point adder
Platform: | Size: 1024 | Author: vijay | Hits:

[VHDL-FPGA-Verilog] Floating-Point-Adder

Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
Platform: | Size: 154624 | Author: 凌音 | Hits:

[VHDL-FPGA-Verilog] fpufiles

Description: floating point adder mul and sub in verilog code
Platform: | Size: 19456 | Author: khosro raja | Hits:

[VHDL-FPGA-Verilog] fpuvhdl_latest

Description: the code describle a floating point adder with verilog
Platform: | Size: 133120 | Author: frank | Hits:

[VHDL-FPGA-Verilog] floating-point-adder

Description: verilog implementation of the floating point adder
Platform: | Size: 2048 | Author: ramtin | Hits:

[VHDL-FPGA-Verilog] add

Description: 浮点加法器的用Verilog实现，32位的浮点加法器-Floating point adder Verilog
Platform: | Size: 1654784 | Author: 王轩 | Hits:

[VHDL-FPGA-Verilog] a-floating-point-adder

Description: 一个浮点加法器，verilog描述，数据格式：高14位为尾数，低四位位指数（带符号数运算）-A floating point adder Verilog description
Platform: | Size: 2048 | Author: 张松 | Hits:

[VHDL-FPGA-Verilog] float

Description: 基于Verilog HDL的32位浮点运算加法器的源代码。-Based on the 32-bit floating point adder in Verilog HDL source code.
Platform: | Size: 1024 | Author: 朱文 | Hits:

[VHDL-FPGA-Verilog] float

Description: 32位浮点加法器 verilog语言编写-32-bit floating-point adder verilog language
Platform: | Size: 1024 | Author: 真 | Hits:

[Software Engineering] xjwbwd

Description: 这个fpadd程序应用verilog语言，实现的功能是简单的浮点加法器。初学的同学们可以一看。-This fpadd program applications verilog language to achieve the function is simple floating point adder. Beginner students can have a look.
Platform: | Size: 1024 | Author: TD | Hits:

[File Format] fpaddmisc-(1)

Description: VERILOG CODE FOR FLOating point adder
Platform: | Size: 2048 | Author: hari | Hits:

[VHDL-FPGA-Verilog] Float_add

Description: 该源码利用Verilog HDL语言成功实现了浮点数的加法运算，包括全部工程以及Verilog 源码，经验证，该程序成功实现了浮点数的加法。-The use of Verilog HDL source language of the successful implementation of floating-point addition operation, including all engineering and Verilog source code, proven, successful implementation of the program the floating point adder.
Platform: | Size: 12144640 | Author: zhu yue | Hits:

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[VHDL-FPGA-Verilog] flowadd

[VHDL-FPGA-Verilog] fadd

[Linux-Unix] fpadd

[source in ebook] fadd

[VHDL-FPGA-Verilog] Floating-Point-Adder

[VHDL-FPGA-Verilog] fpufiles

[VHDL-FPGA-Verilog] fpuvhdl_latest

[VHDL-FPGA-Verilog] floating-point-adder

[VHDL-FPGA-Verilog] add

[VHDL-FPGA-Verilog] a-floating-point-adder

[VHDL-FPGA-Verilog] float

[VHDL-FPGA-Verilog] float

[Software Engineering] xjwbwd

[File Format] fpaddmisc-(1)

[VHDL-FPGA-Verilog] Float_add

[VHDL-FPGA-Verilog] adder

[Other] Fixed-Floating-Point-Adder-Multiplier-master

[VHDL-FPGA-Verilog] FP_adder

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